CY8CLED04D01_1105 Datasheet, PDF (29/55 Pages) Cypress Semiconductor – PowerPSoC Intelligent LED Driver floating load buck-boost, and boost

CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
14. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X,
CY8CLED03G01, CY8CLED02D01, and CY8CLED01D01 of the PowerPSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/powerpsoc.
Specifications for Industrial rated devices are valid for –40 °C  T_A  85 °C, T_J  115 °C and for Extended Temperature rated devices
for –40 °C  T_A  105 °C, T_J  125 °C, except where noted.
14.1 Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested.
Table 14-1. Absolute Maximum Ratings
Symbol
T_STG
T_A
V_DD,
AV_DD,
GDV_DD
V_IO
V_IO2
V_FET
V_REGIN
V_CSP,V_CSN
V_SENSE
I_MAIO
I_MIO
LU
ESD
SR_REGIN
Description
Storage temperature
Min
Typ
–55
–
Ambient temperature with power applied –40
–
-40
–
Supply voltage on V_DD, AV_DD, and
GDV_DD
–0.5
–
DC input voltage
V_SS – 0.5 –
DC voltage applied to tristate
V_SS – 0.5 –
Maximum voltage from power Switch
–
–
(SWx) to Power FET Ground (PGNDx)
Maximum voltage on SREGHVIN Pin
–
–
relative to V_SS
Maximum voltage applied to CSA pins
–0.5
–
relative to V_SS
Maximum input differential voltage across –1.0
–
CSA input
Maximum current into any port pin
configured as analog driver
–50
–
Maximum current into any port and
function pin
–25
–
Latch up current
200
–
Electrostatic Discharge Voltage
2000
–
Ramp Rate for the SREGHVIN pin
–
–
Max
+115
+85
+105
+6.0
Units
°C
°C
°C
V
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage temper-
ature is 0 °C to 50 °C.
T_J 115 °C (Industrial rated)
T_J 125 °C (Extended Temper-
ature rated)
Relative to V_SS, AV_SS, and
GDV_SS respectively
V_DD + 0.5
V_DD + 0.5
36^[13]
36^[13]
V Applies only to GPIO and FN0
pins
V
V PGNDx is connected to GDV_SS
V
36^[13]
V
1.0
V
+50
mA
+50
mA
–
mA JESD78A Conformal
–
V Human Body Model ESD.
32
V/s
SR_CSP
Ramp Rate for the CSPx pins
SR_HV_DD-FLB High Voltage Supply Ramp Rate for
Floating Load Buck Configuration
–
–
3.2
V/s
–
–
15
V/ms For other topologies, to enable
operation with faster ramp rates,
or if the LED string voltage is
< 6.5 V, see the PowerPSoC
Technical Reference Manual.
SRV_DD-EXT External V_DD Supply Ramp Rate (V_DD,
–
–
0.2
V/s Applies only when powered by a
AV_DD, and GDV_DD pins)
source other than the Built-in
Switching Regulator
Note
13. Stresses beyond the “Absolute Maximum Ratings” on page 29 may cause permanent damage to the device. You must ensure that the Absolute Maximum Ratings
are NEVER exceeded. Functional operation is not implied under any conditions beyond the “Electrical Characteristics” on page 30 onwards. Extended exposure to
“Absolute Maximum Ratings” on page 29 may affect reliability of the device.
Document Number: 001-46319 Rev. *N
Page 29 of 55
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