CY7C63221A Datasheet, PDF (29/49 Pages) Cypress Semiconductor – enCoRe USB Low-speed USB Peripheral Controller

FOR
FOR
enCoRe™ USB
CY7C63221/31A
Bit #
7
6
5
4
3
2
1
0
Bit Name
Timer [7:0]
Read/Write
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 17-1. Timer LSB Register (Address 0x24)
Bit [7:0]: Timer lower 8 bits
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
Timer [11:8]
Read/Write
-
-
-
-
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Figure 17-2. Timer MSB Register (Address 0x25)
Bit [7:4]: Reserved
Bit [3:0]: Timer upper 4 bits
1.024-ms interrupt
128-µs interrupt
11 10 9 8 7 6 5 4 3 2 1 0
1 MHz clock
L3 L2 L1 L0
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
8
Figure 17-3. Timer Block Diagram
To Timer Registers
18.0 Processor Status and Control Register
Bit #
7
6
5
4
3
2
1
0
Bit Name
IRQ
Watchdog
Bus
LVR/BOR Suspend Interrupt Reserved
Run
Pending
Reset
Interrupt
Reset
Enable
Event
Sense
Read/Write
R
R/W
R/W
R/W
R/W
R
-
R/W
Reset
0
1
0
1
0
0
0
1
Figure 18-1. Processor Status and Control Register (Address 0xFF)
Bit 7: IRQ Pending
When an interrupt is generated, it is registered as a pending interrupt. The interrupt will remain pending until its interrupt enable
bit is set (Figure 19-1 and Figure 19-2) and interrupts are globally enabled (Bit 2, Processor Status and Control Register). At
that point the internal interrupt handling sequence will clear the IRQ Pending bit until another interrupt is detected as pending.
This bit is only valid if the Global Interrupt Enable bit is disabled.
Document #: 38-08028 Rev. *A
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