CY8CTMA120 Datasheet, PDF (28/35 Pages) Cypress Semiconductor – TrueTouch™ Multi-Touch All-Point Touchscreen Controller

CY8CTMA120
Table 31. 3.3V AC Analog Output Buffer Specifications
Symbol
T_ROB
T_SOB
SR_ROB
SR_FOB
BW_OBSS
BW_OBLS
Description
Rising Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step,
100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step,
100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mV_pp, 3dB BW,
100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1V_pp, 3dB BW, 100pF
Load
Power = Low
Power = High
Min
–
–
–
–
0.5
0.5
0.5
0.5
0.7
0.7
200
200
Typ
–
–
–
–
–
–
–
–
–
–
–
–
Max
3.8
3.8
2.6
2.6
–
–
–
–
–
–
–
–
Units
μs
μs
μs
μs
V/μs
V/μs
V/μs
V/μs
MHz
MHz
kHz
kHz
Notes
AC Programming Specifications
Table 32 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for
design guidance only.
Table 32. AC Programming Specifications
Symbol
T_RSCLK
T_FSCLK
T_SSCLK
T_HSCLK
F_SCLK
T_ERASEB
T_WRITE
T_DSCLK
T_DSCLK3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
30
–
–
Max
20
20
–
–
8
–
–
45
50
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Document Number: 001-46901 Rev. *C
Page 28 of 35
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