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CY8CNP102E Datasheet, PDF (28/38 Pages) Cypress Semiconductor – Nonvolatile Programmable System-on-Chip(PSoC® NV)
PRELIMINARY CY8CNP102B, CY8CNP102E
AC Electrical Characteristics
The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature
range: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design
guidance only.
AC Chip Level Specifications
Table 33. 5V AC Chip Level Specifications (CY8CNP102E)
Symbol
Description
Min
FIMO24
Internal Main Oscillator Frequency for 24 MHz 23.4
FIMO6
Internal Main Oscillator Frequency for 6 MHz 5.75
FCPU1
F48M
F24M
F32K1
F32K2
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
0.93
0
0
15
–
FPLL
PLL Frequency
–
Jitter24M2 24 MHz Period Jitter (PLL)
–
TPLLSLEW
PLL Lock Time
0.5
TPLLSLEWLOW PLL Lock Time for Low Gain Setting
0.5
TOS
External Crystal Oscillator Startup to 1%
–
TOSACC
External Crystal Oscillator Startup to 100 ppm –
Jitter32k
32 kHz Period Jitter
–
TXRST
External Reset Pulse Width
10
DC24M
24 MHz Duty Cycle
40
Step24M
24 MHz Trim Step Size
–
Fout48M
48 MHz Output Frequency
46.8
Jitter24M1 24 MHz Period Jitter (IMO)
–
FMAX
Maximum frequency of signal on row input or
–
row output.
TRAMP
Supply Ramp Time
0
Typ Max
24 24.6[4, 5, 6]
6 6.35[4 , 5, 6]
24 24.6[4, 5]
48 49.2[4, 5, 7]
24
32
32.768
24.6[5, 7]
64
–
23.986 –
–
600
–
10
–
50
250
500
300
600
100
–
50
50
48.0
–
60
–
49.2[4,6]
600
–
12.3
Units
MHz
MHz
MHz
MHz
MHz
kHz
kHz
MHz
ps
ms
ms
ms
ms
ns
μs
%
kHz
MHz
ps
MHz
Notes
Trimmed for 5V operation
using factory trim values.
See Figure 5 on page 9.
SLIMO Mode = 0.
Trimmed for 5V operation
using factory trim values.
See Figure 5 on page 9.
SLIMO Mode = 1.
Refer to AC Digital Block
Specifications on page 30.
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
A multiple (x732) of crystal
frequency.
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the Tosacc period. Correct
operation assumes a
properly loaded 1 uW
maximum drive level 32.768
kHz crystal.
Trimmed. Using factory trim
values.
–
–
μs
Document #: 001-43991 Rev. *D
Page 28 of 38
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