CY8C28243_12 Datasheet, PDF (28/78 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
Table 18. CY8C28x45 Register Map Bank 0 Table: User Space
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex)
PRT0DR
00
RW DBC20DR0
40
#
ASC10CR0
80
RW RDI2RI
C0
PRT0IE
01
RW DBC20DR1
41
W ASC10CR1
81
RW RDI2SYN
C1
PRT0GS
02
RW DBC20DR2
42
RW ASC10CR2
82
RW RDI2IS
C2
PRT0DM2
03
RW DBC20CR0
43
#
ASC10CR3
83
RW RDI2LT0
C3
PRT1DR
04
RW DBC21DR0
44
#
ASD11CR0
84
RW RDI2LT1
C4
PRT1IE
05
RW DBC21DR1
45
W ASD11CR1
85
RW RDI2RO0
C5
PRT1GS
06
RW DBC21DR2
46
RW ASD11CR2
86
RW RDI2RO1
C6
PRT1DM2
07
RW DBC21CR0
47
#
ASD11CR3
87
RW RDI2DSM
C7
PRT2DR
08
RW DCC22DR0
48
#
ASC12CR0
88
RW
C8
PRT2IE
09
RW DCC22DR1
49
W ASC12CR1
89
RW
C9
PRT2GS
0A
RW DCC22DR2
4A
RW ASC12CR2
8A
RW
CA
PRT2DM2
0B
RW DCC22CR0
4B
#
ASC12CR3
8B
RW
CB
PRT3DR
0C
RW DCC23DR0
4C
#
ASD13CR0
8C
RW
CC
PRT3IE
0D
RW DCC23DR1
4D
W ASD13CR1
8D
RW
CD
PRT3GS
0E
RW DCC23DR2
4E
RW ASD13CR2
8E
RW
CE
PRT3DM2
0F
RW DCC23CR0
4F
#
ASD13CR3
8F
RW
CF
PRT4DR
10
RW
50
ASD20CR0
90
RW CUR_PP
D0
PRT4IE
11
RW
51
ASD20CR1
91
RW STK_PP
D1
PRT4GS
12
RW
52
ASD20CR2
92
RW
D2
PRT4DM2
13
RW
53
ASD20CR3
93
RW IDX_PP
D3
PRT5DR
14
RW
54
ASC21CR0
94
RW MVR_PP
D4
PRT5IE
15
RW
55
ASC21CR1
95
RW MVW_PP
D5
PRT5GS
16
RW
56
ASC21CR2
96
RW I2C0_CFG
D6
PRT5DM2
17
RW
57
ASC21CR3
97
RW I2C0_SCR
D7
18
58
ASD22CR0
98
RW I2C0_DR
D8
19
59
ASD22CR1
99
RW I2C0_MSCR
D9
1A
5A
ASD22CR2
9A
RW INT_CLR0
DA
1B
5B
ASD22CR3
9B
RW INT_CLR1
DB
1C
5C
ASC23CR0
9C
RW INT_CLR2
DC
1D
5D
ASC23CR1
9D
RW INT_CLR3
DD
1E
5E
ASC23CR2
9E
RW INT_MSK3
DE
1F
5F
ASC23CR3
9F
RW INT_MSK2
DF
DBC00DR0
20
#
AMX_IN
60
RW DEC0_DH
A0
RC INT_MSK0
E0
DBC00DR1
21
W AMUX_CFG
61
RW DEC0_DL
A1
RC INT_MSK1
E1
DBC00DR2
22
RW CLK_CR3
62
RW DEC1_DH
A2
RC INT_VC
E2
DBC00CR0
23
#
ARF_CR
63
RW DEC1_DL
A3
RC RES_WDT
E3
DBC01DR0
24
#
CMP_CR0
64
#
DEC2_DH
A4
RC I2C1_SCR
E4
DBC01DR1
25
W ASY_CR
65
#
DEC2_DL
A5
RC I2C1_MSCR
E5
DBC01DR2
26
RW CMP_CR1
66
RW DEC3_DH
A6
RC DEC_CR0*
E6
DBC01CR0
27
#
I2C1_DR
67
RW DEC3_DL
A7
RC DEC_CR1*
E7
DCC02DR0
28
#
68
MUL1_X
A8
W MUL0_X
E8
DCC02DR1
29
W
69
MUL1_Y
A9
W MUL0_Y
E9
DCC02DR2
2A
RW SADC_DH
6A
RW MUL1_DH
AA
R
MUL0_DH
EA
DCC02CR0
2B
#
SADC_DL
6B
RW MUL1_DL
AB
R
MUL0_DL
EB
DCC03DR0
2C
#
TMP_DR0
6C
RW ACC1_DR1
AC
RW ACC0_DR1
EC
DCC03DR1
2D
W TMP_DR1
6D
RW ACC1_DR0
AD
RW ACC0_DR0
ED
DCC03DR2
2E
RW TMP_DR2
6E
RW ACC1_DR3
AE
RW ACC0_DR3
EE
DCC03CR0
2F
#
TMP_DR3
6F
RW ACC1_DR2
AF
RW ACC0_DR2
EF
DBC10DR0
30
#
ACB00CR3
70
RW RDI0RI
B0
RW
F0
DBC10DR1
31
W ACB00CR0
71
RW RDI0SYN
B1
RW
F1
DBC10DR2
32
RW ACB00CR1
72
RW RDI0IS
B2
RW
F2
DBC10CR0
33
#
ACB00CR2
73
RW RDI0LT0
B3
RW
F3
DBC11DR0
34
#
ACB01CR3
74
RW RDI0LT1
B4
RW
F4
DBC11DR1
35
W ACB01CR0
75
RW RDI0RO0
B5
RW
F5
DBC11DR2
36
RW ACB01CR1
76
RW RDI0RO1
B6
RW
F6
DBC11CR0
37
#
ACB01CR2
77
RW RDI0DSM
B7
RW CPU_F
F7
DCC12DR0
38
#
ACB02CR3
78
RW RDI1RI
B8
RW
F8
DCC12DR1
39
W ACB02CR0
79
RW RDI1SYN
B9
RW
F9
DCC12DR2
3A
RW ACB02CR1
7A
RW RDI1IS
BA
RW
FA
DCC12CR0
3B
#
ACB02CR2
7B
RW RDI1LT0
BB
RW
FB
DCC13DR0
3C
#
ACB03CR3
7C
RW RDI1LT1
BC
RW DAC1_D
FC
DCC13DR1
3D
W ACB03CR0
7D
RW RDI1RO0
BD
RW DAC0_D
FD
DCC13DR2
3E
RW ACB03CR1
7E
RW RDI1RO1
BE
RW CPU_SCR1
FE
DCC13CR0
3F
#
ACB03CR2
7F
RW RDI1DSM
BF
RW CPU_SCR0
FF
Blank fields are Reserved and should not be accessed.
# Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
#
#
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
RW
#
#
Document Number: 001-48111 Rev. *K
Page 28 of 78