CY8C24633 Datasheet, PDF (28/35 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C24633
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. AC Low Power Comparator Specifications
Symbol
Description
T_RLPC LPC response time
Min Typ Max Units
Notes
–
–
50
μs ≥ 50 mV overdrive comparator
reference set within V_REFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 28. 5V and 3.3V AC Digital Block Specifications
Symbol
Description
Timer Capture Pulse Width
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Counter Enable Pulse Width
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Dead
Band
Kill Pulse Width:
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
Maximum Frequency
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
SPIM
Maximum Input Clock Frequency
Min Typ
50^[16]
–
–
–
–
–
50^[16]
–
–
–
–
–
20
–
50^[16]
–
50^[16]
–
–
–
–
–
–
–
–
–
SPIS
Maximum Input Clock Frequency
–
–
Width of SS_ Negated Between Transmis- 50^[16]
–
sions
Trans- Maximum Input Clock Frequency
–
–
mitter
Maximum Input Clock Frequency with Vdd Š –
–
4.75V, 2 Stop Bits
Receiver Maximum Input Clock Frequency
–
–
Maximum Input Clock Frequency with Vdd Š –
–
4.75V, 2 Stop Bits
Max Units
Notes
–
ns
49.2 MHz 4.75V < Vdd < 5.25V.
24.6 MHz
–
ns
49.2 MHz 4.75V < Vdd < 5.25V.
24.6 MHz
–
ns
–
ns
–
ns
49.2 MHz 4.75V < Vdd < 5.25V.
49.2 MHz 4.75V < Vdd < 5.25V.
24.6 MHz
8.2 MHz Maximum data rate at 4.1 MHz due to
2 x over clocking.
4.1 MHz
–
ns
24.6 MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking.
49.2 MHz Maximum data rate at 6.15 MHz due
to 8 x over clocking.
24.6 MHz Maximum data rate at 3.08 MHz due
to 8 x over clocking.
49.2 MHz Maximum data rate at 6.15 MHz due
to 8 x over clocking.
Note
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-20160 Rev. *B
Page 28 of 35
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