CY8C20134 Datasheet, PDF (28/47 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
Table 30. 2.7-V AC Characteristics of the I²C SDA and SCL Pins (Fast Mode not Supported)
Symbol
F_SCLI2C
t_HDSTAI2C
t_LOWI2C
t_HIGHI2C
t_SUSTAI2C
t_HDDATI2C
t_SUDATI2C
t_SUSTOI2C
t_BUFI2C
t_SPI2C
Description
SCL clock frequency
Hold time (repeated) START condition. After this period,
the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated start condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
Standard Mode
Min
Max
0
100
4.0
–
4.7
–
4.0
–
4.7
–
0
–
250
–
4.0
–
4.7
–
–
–
Fast Mode
Min
Max
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 12. Definition for Timing for Fast/Standard Mode on the I²C Bus
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
I2C_SDA
I2C_SCL
T_SUDATI2C
T_HDSTAI2C
T_HDDATI2C^TSUSTAI2C
T_SPI2C
T_BUFI2C
T_HIGHI2C T_LOWI2C
S
START Condition
T_SUSTOI2C
Sr
P
S
Repeated START Condition
STOP Condition
Document Number: 001-05356 Rev. *N
Page 28 of 47
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