CY7C2262XV18 Datasheet, PDF (28/29 Pages) Cypress Semiconductor – 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2262XV18, CY7C2264XV18
Document History Page
Document Title: CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR^® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle
Read Latency) with ODT
Document Number: 001-70330
Rev.
ECN No.
Orig. of Submission
Change
Date
Description of Change
**
3377111 VIDB 09/20/2011 New data sheet.
*A
3532265 PRIT / 02/22/2012 Changed status from Preliminary to Final.
GOPA
*B
3783098 PRIT 10/25/2012 Updated Application Example (Updated Figure 2).
Updated TAP Electrical Characteristics (Updated Note 14).
Updated TAP AC Switching Characteristics (Updated Note 17).
Updated TAP Timing and Test Conditions (Updated Note 18 and updated
Figure 3).
Updated Thermal Resistance (Changed value of Theta JA parameter from
26.65 °C/W to 14.84 °C/W (for Test Condition "With Still Air (0 m/s)") for
165-ball FBGA Package, changed value of Theta JA parameter from
22.76 °C/W to 13.68 °C/W (for Test Condition "With Air flow (1 m/s)") for
165-ball FBGA Package, changed value of Theta JC parameter from
4.31 °C/W to 5.1 °C/W for 165-ball FBGA Package).
Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).
Document Number : 001-70330 Rev. *B
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