CY14V101QS Datasheet, PDF (28/55 Pages) Cypress Semiconductor – 1-Mbit (128K × 8) Quad SPI nvSRAM

CY14V101QS
System Resources Instructions
Software Reset (RESET) Instruction
RESET instruction resets the whole device and makes it ready
to receive commands. The I/O mode is configured to SPI. All
nonvolatile registers or nonvolatile register bits maintain their
values. All volatile registers or volatile register bits default to logic
‘0’. It takes t_RESET time to complete. No STORE/RECALL
operations are performed. To initiate the software reset process,
the reset enable (RSTEN) instruction is required. This ensures
protection against any inadvertent resets. Thus software reset is
a sequence of two commands.
Note Any command other than RESET following the RSTEN
command, will clear the reset enable condition and prevent a
later RESET command from being recognized.
Note If WIP (SR[0]) bit is high and the RSTEN/RESET instruction
is entered, the device ignores the RSTEN/RESET instruction.
Note The functionalities of WP and NC (I/O3) are controlled by
the Quad bit CR[1] in Configuration register. If Quad bit is set to
logic ‘1’, WP and NC (I/O3) are configured as I/O2 and I/O3
respectively. Otherwise, WP and NC (I/O3) functionality is
configured.
Table 9 summarizes the device’s state after software reset.
Table 9. Software Reset State
State 1
STANDBY
State 2
State 3
Software RESET
STANDBY
I/O Mode & Register Bits
I/O Mode: SPI
SRWD SR[7]: Same as State 1
SNL SR[6]: Same as State 1
TBPROT SR[5]: Same as State 1
BP2 SR[4]: Same as State 1
BP1 SR[3]: Same as State 1
BP0 SR[2]: Same as State 1
WEL SR[1]: 0
WIP SR[0]: 0
QUAD CR[1]: Same as State 1
Figure 42. RESET Instruction in SPI Mode
Figure 43. RESET Instruction in DPI Mode
CS
CS
SCK
SI
SO
X
0
1
1
0
0
1
1
0
X
hi-Z
Opcode (66)
CS
SCK
I/O0 ^hi-Z
1
0
1
0
hi-Z
I/O1 ^hi-Z
0
1
0
1
hi-Z
Opcode (66h)
CS
SCK
SI
SO
X
1
0
0
1
1
0
0
1
X
hi-Z
Opcode (99h)
SCK
I/O0
hi-Z
0
1
0
1
hi-Z
I/O1
hi-Z
1
0
1
0
hi-Z
Opcode (99h)
Document Number: 001-85257 Rev. *K
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