CY14C512PA Datasheet, PDF(28/43 Page) Cypress Semiconductor – 512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC

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CY14C512PA Datasheet, PDF (28/43 Pages) Cypress Semiconductor – 512-Kbit (64 K x 8) SPI nvSRAM with Real Time Clock Full-featured RTC

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CY14C512PA

CY14B512PA

CY14E512PA

Table 12. Register Map Detail (continued)

0x07

WDS

WDW

WDT

0x06

WIE

AIE

PFE

SQWE

H/L

P/L

SQ1, SQ0

0x05

0x04

Description

Watchdog Timer

WDS

WDW

WDT

Watchdog Strobe. Setting this bit to â1â reloads and restarts the watchdog timer. Setting the bit to â0â has no effect. The

bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a â0â.

Watchdog Write Enable. Setting this bit to â1â disables any WRITE to the watchdog timeout value (D5âD0). This enables

the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to â0â allows bits D5âD0 to

be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in

Watchdog Timer on page 22.

Watchdog Timeout Selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a

multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting

of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was

set to â0â on a previous cycle.

Interrupt Status/Control

WIE

AIE

PFE

SQWE

H/L

P/L

SQ1

SQ0

Watchdog Interrupt Enable. When set to â1â and a watchdog timeout occurs, the watchdog timer drives the INT pin and

the WDF flag. When set to â0â, the watchdog timeout affects only the WDF flag.

Alarm Interrupt Enable. When set to â1â, the alarm match drives the INT pin and the AF flag. When set to â0â, the alarm

match only affects the AF flag.

Power Fail Enable. When set to â1â, the alarm match drives the INT pin and the PF flag. When set to â0â, the power fail

monitor affects only the PF flag.

Square Wave Enable. When set to â1â, a square wave is driven on the INT pin with frequency programmed using SQ1

and SQ0 bits. The square wave output takes precedence over interrupt logic. If the SQWE bit is set to â1â. when an

enabled interrupt source becomes active, only the corresponding flag is raised and the INT pin continues to drive the

square wave.

High/Low. When set to â1â, the INT pin is driven active HIGH. When set to â0â, the INT pin is open drain, active LOW.

Pulse/Level. When set to â1â, the INT pin is driven active (determined by H/L) by an interrupt source for approximately

200 ms. When set to â0â, the INT pin is driven to an active level (as set by H/L) until the flags register is read.

SQ1, SQ0. These bits are used to decide the frequency of the Square wave on the INT pin output when SQWE bit is

set to â1â. The following is the frequency output for each combination of (SQ1, SQ0):

(0, 0) - 1 Hz

(0, 1) - 512 Hz

(1, 0) - 4096 Hz

(1, 1) - 32768 Hz

Alarm - Day

10s alarm date

Alarm date

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

Match. When this bit is set to â0â, the date value is used in the alarm match. Setting this bit to â1â causes the match circuit

to ignore the date value.

Alarm - Hours

10s alarm hours

Alarm hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

Match. When this bit is set to â0â, the hours value is used in the alarm match. Setting this bit to â1â causes the match

circuit to ignore the hours value.

Document #: 001-65268 Rev. *B

Page 28 of 43

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