CY8C29466_12 Datasheet, PDF (27/35 Pages) Cypress Semiconductor – Automotive . Extended Temperature PSoC® Programmable System-on-Chip

CY8C29466, CY8C29666
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T_A  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 23. AC Analog Output Buffer Specifications
Symbol
Description
Min Typ Max Units
T_ROB
Rising Settling Time to 0.1%, 1 V Step, 100pF Load
Power = Low
Power = High
–
–
3
s
–
–
3
s
T_SOB
Falling Settling Time to 0.1%, 1 V Step, 100pF Load
Power = Low
Power = High
–
–
3
s
–
–
3
s
SR_ROB Rising Slew Rate (20% to 80%), 1 V Step, 100 pF Load
Power = Low
0.6
–
Power = High
0.6
–
– V/s
– V/s
SR_FOB Falling Slew Rate (80% to 20%), 1 V Step, 100 pF Load
Power = Low
0.6
–
Power = High
0.6
–
– V/s
– V/s
BW_OB Small Signal Bandwidth, 20mV_pp, 3dB BW, 100 pF Load
Power = Low
0.8
–
Power = High
0.8
–
– MHz
– MHz
BW_OB Large Signal Bandwidth, 1 V_pp, 3dB BW, 100 pF Load
Power = Low
300 –
Power = High
300 –
–
kHz
–
kHz
Notes
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T_A  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 24. AC External Clock Specifications
Symbol
F_OSCEXT
–
–
–
Description
Frequency
High Period
Low Period
Power Up IMO to Switch
Min Typ Max Units
0.093 – 24.24 MHz
20.6
–
–
ns
20.6
–
–
ns
150
–
–
s
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C  T_A  125 °C. Typical parameters apply to 5 V at 25 °C and are for design guidance only.
Table 25. AC Programming Specifications
Symbol
Description
Min Typ Max Units
Notes
T_RSCLK Rise Time of SCLK
1
T_FSCLK Fall Time of SCLK
1
T_SSCLK Data Set up Time to Falling Edge of SCLK
40
T_HSCLK Data Hold Time from Falling Edge of SCLK
40
F_SCLK Frequency of SCLK
0
T_ERASEB Flash Erase Time (Block)
–
T_WRITE Flash Block Write Time
–
T_DSCLK Data Out Delay from Falling Edge of SCLK
–
T_PRGH Total Flash Block Program Time (T_ERASEB + T_WRITE),
–
Hot
T_PRGC Total Flash Block Program Time (T_ERASEB + T_WRITE),
–
Cold
–
20
ns
–
20
ns
–
–
ns
–
–
ns
–
8
MHz
10
40^[10]
ms
40
160^[10]
ms
–
50
ns
–
100^[10]
ms T_J  0 °C
–
200^[10]
ms T_J  0 °C
Document Number: 38-12026 Rev. *M
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