CY8C24223A_13 Datasheet, PDF (27/50 Pages) Cypress Semiconductor – Automotive PSoC® Programmable System-on-Chip

CY8C24223A, CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  T_A  85 °C, 3.0 V to 3.6 V and –40 °C  T_A  85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 21. AC Chip-Level Specifications
Symbol
F_IMO24
F_IMO6
F_CPU1
F_CPU2
F_BLK5
F_BLK33
F_32K1
F_32KU
F_32K2
F_PLL
t_PLLSLEW
t_PLLSLEWSLOW
t_OS
t_OSACC
t_XRST
DC24M
DC_ILO
Step24M
Fout48M
F_MAX
SR_POWERUP
t_POWERUP
t_{JIT_IMO} ^[15]
t_{JIT_PLL} ^[15]
Description
IMO frequency for 24 MHz
Min Typ
22.8^[13] 24
IMO frequency for 6 MHz
5.5^[13]
6
CPU frequency (5 V V_DD nominal) 0.089^[13] –
CPU frequency (3.3 V V_DD
nominal)
0.089^[13] –
Digital PSoC block frequency (5 V
0
–
V_DD nominal)
Digital PSoC block frequency (3.3
0
–
V V_DD nominal)
ILO frequency
15
32
ILO untrimmed frequency
5
–
External crystal oscillator
–
32.76
8
PLL frequency
–
23.98
6
PLL lock time
0.5
–
PLL lock time for low gain setting
0.5
–
External crystal oscillator startup to
–
1%
1700
External crystal oscillator startup to
–
100 ppm
2800
External reset pulse width
24 MHz duty cycle
ILO duty cycle
24 MHz trim step size
48 MHz output frequency
Maximum frequency of signal on
row input or row output.
Power supply slew rate
Time between end of POR state
and CPU code execution
24 MHz IMO cycle-to-cycle jitter
(RMS)
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
24 MHz IMO period jitter (RMS)
PLL cycle-to-cycle jitter (RMS)
PLL long term N cycle-to-cycle
jitter (RMS)
PLL period jitter (RMS)
10
40
20
–
45.6^[13]
–
–
50
50
50
48.0
–
–
–
–
16
–
200
–
300
–
100
–
200
–
300
–
100
Max
25.2^[13]
6.5^[13]
25.2^[13]
12.6^[13]
50.4^[13,14]
25.2^[13,14]
64
100
–
–
10
50
2620
3800
–
60
80
–
50.4^[13]
12.6^[13]
250
100
700
900
400
800
1200
700
Units
Notes
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 0.
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 6 on page 13. SLIMO
mode = 1.
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
MHz Minimum CPU frequency is 0.022 MHz when
SLIMO mode = 0.
MHz Refer to AC Digital Block Specifications on
page 32.
MHz Refer to AC Digital Block Specifications on
page 32.
kHz This specification applies when the ILO has
been trimmed.
kHz After a reset and before the M8C processor
starts to execute, the ILO is not trimmed.
kHz Accuracy is capacitor and crystal dependent.
50% duty cycle.
MHz Is a multiple (x732) of crystal frequency.
ms Refer to Figure 7 on page 28.
ms Refer to Figure 8 on page 28.
ms Refer to Figure 9 on page 28.
ms
s
%
%
kHz
MHz
MHz
The crystal oscillator frequency is within 100
ppm of its final value by the end of the t_OSACC
period. Correct operation assumes a properly
loaded 1 µW maximum drive level 32.768 kHz
crystal. 3.0 V  V_DD  5.25 V, –40 C  T_A  85 C.
Trimmed. Using factory trim values.
V/ms V_DD slew rate during power up.
ms Power up from 0 V.
ps
ps N = 32
ps
ps
ps N = 32
ps
Notes
13. Accuracy derived from IMO with appropriate trim for V_DD range.
14. See the individual user module data sheets for information on maximum frequencies for user modules.
15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-52469 Rev. *H
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