CYD09S18V18-167BBXI Datasheet, PDF (26/53 Pages) Cypress Semiconductor – FullFlex Synchronous SDR Dual Port SRAM

CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Switching Characteristics
Over the Operating Range
Table 12. SDR Mode, Signals Affected by DLL
Description
DLL ON (LOWSPD=1)^[46]
DLL OFF (LOWSPD=0)^[46]
Parameter
t_CD2[49]
C rise to DQ valid for pipelined
mode
t_CCQ[49]
C rise to CQ rise
t_CKHZ2[44, ^49] C rise to DQ output high Z in
pipelined mode
t_CKLZ2[44, ^49] C rise to DQ output low Z in
pipelined mode
-200
Min
Max
–
3.30^{[45, 48]}
1.00
1.00
3.30 ^[48]
3.30^{[45, 48]}
1.00
–
-167
Min
Max
–
4.00^{[45, 48]}
1.00
1.00
4.00^[48]
4.00^{[45, 48]}
1.00
–
Min
–
1.00
1.00
1.00
Max
6.00^{[45, 48]}
Unit
ns
6.00^[48]
ns
6.00^{[45, 48]} ns
–
ns
Table 13. SDR Mode
Parameter
Description
f_MAX
Maximum operating frequency for pipelined mode
(PIPELINED)
f_MAX (FLOW Maximum operating frequency for flow through mode
THROUGH)
t_CYC
C clock cycle time for pipelined mode
(PIPELINED)
t_CYC (FLOW X C clock cycle time for flow through mode
THROUGH)
t_CKD
t_SD
C clock duty time
Data input setup time to C HSTL
rise
1.8 V LVCMOS
t_HD[47]
t_SAC
2.5 V LVCMOS
3.3 V LVTTL
Data input hold time after C rise
Address and control input HSTL
setup time to C rise
1.8 V L VCMOS
t_HAC[47]
t_OE
t_OLZ[44]
2.5 V LVCMOS
3.3 V LVTTL
Address and control input hold time after C rise
Output enable to data valid
OE to low Z
-200
Min
Max
100
200
-167
Min
Max
100
167
Unit
MHz
–
5.00^[48]
13.00^[48]
77
10.00
–
–
6.00^[48]
15.00^[48]
66.7 MHz
10.00 ns
–
ns
45
55
45
55
%
1.50^{[45, 48]}
–
1.70^{[45, 48]}
–
ns
1.75^{[45, 48]}
–
1.95^{[45, 48]}
ns
0.5
–
0.5
–
ns
1.50^{[45, 47, 48]}
–
1.70^{[45, 47, 48]}
–
ns
1.75^{[45, 47, 48]}
–
1.95^{[45, 47, 48]}
–
ns
0.50
–
1.00
–
4.40^{[45, 48]}
–
0.60
–
1.00
–
ns
5.00^{[45, 48]} ns
–
ns
Notes
44. Parameters specified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25.
45. For the x18 devices, add 200 ps to this parameter in Table 13.
46. Test conditions assume a signal transition time of 2 V/ns.
47. Add 300 ps to this timing for 36M devices.
48. Add 15% to this parameter if a VCORE of 1.5 V is used.
49. This parameter assumes input clock cycle to cycle jitter of ± 0 ps.
Document Number: 38-06082 Rev. *O
Page 26 of 53