CY7C63722C_11 Datasheet, PDF (26/53 Pages) Cypress Semiconductor – enCoRe USB Combination Low-Speed USB and PS/2 Peripheral Controller

CY7C63722C
CY7C63723C
CY7C63743C
Timer Capture Registers
Four 8-bit capture timer registers provide both rising- and falling-edge event timing capture on two pins. Capture Timer A is connected
to Pin 0.0, and Capture Timer B is connected to Pin 0.1. These can be used to mark the time at which a rising or falling event occurs
at the two GPIO pins. Each timer will capture eight bits of the free-running timer into its Capture Timer Data Register if a rising or
falling edge event that matches the specified rising or falling edge condition at the pin. A prescaler allows selection of the capture
timer tick size. Interrupts can be individually enabled for the four capture registers. A block diagram is shown in Figure .
Figure 27. Capture Timers Block Diagram
Free-running Timer
11 10 9 8
76543210
1 MHz
Clock
First Edge Hold
Bit 7, Reg 0x44
Prescaler
Mux
GPIO
P0.0
Rising
Edge
Detect
Falling
Edge
Detect
GPIO
P0.1
Rising
Edge
Detect
Falling
Edge
Detect
Capture A Rising Int Enable
Bit 0, Reg 0x44
Capture A Falling Int Enable
Bit 1, Reg 0x44
Capture B Rising Int Enable
Bit 2, Reg 0x44
Capture B Falling Int Enable
Bit 3, Reg 0x44
8-bit Capture Registers
Timer A Rising Edge Time
Timer A Falling Edge Time
Timer B Rising Edge Time
Timer B Falling Edge Time
Capture Timer A Interrupt Request
Capture Timer B Interrupt Request
Document #: 38-08022 Rev. *E
Page 26 of 53
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