CY7C43644 Datasheet, PDF (26/39 Pages) Cypress Semiconductor – 1K/4K x36 x2 Bidirectional Synchronous FIFO with Bus Matching

CY7C43644
CY7C43664
CY7C43684
Switching Waveforms (continued)
EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY standard Mode) ^[39]
CLKA
t_CLK
t_CLKH t_CLKL
CSA
W/RA
MBA
ENA
LOW
HIGH
t_ENSt_ENH
t_ENSt_ENH
FFA/IRA
A_0–35
HIGH
CLKB
t_DS t_DH
W1
t_SKEW1[41] ^tCLKH
t_CLKL
EFB/ORB
FIFO1 Empty
t_CLK
t_REF
t_REF
CSB
LOW
W/RB
HIGH
MBB
ENB
B_0–35
LOW
t_ENSt_ENH
t_A
W1
Note:
41. t_SKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than t_SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Document #: 38-06022 Rev. *B
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