CY7C1516JV18_09 Datasheet, PDF (26/26 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 2-Word Burst Architecture

CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
Document History Page
Document Title: CY7C1516JV18/CY7C1527JV18/CY7C1518JV18/CY7C1520JV18, 72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 001-12559
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
** 808457 See ECN
VKN
New Data Sheet
*A 1273883 See ECN
VKN
Removed t_SD footnote
Updated Logic block diagram for x18 and x36 parts
*B 1462589 See ECN VKN/AESA Converted from preliminary to final
Updated I_DD/I_SB specs
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed t_CYC max spec to 8.4ns
*C 2189567 See ECN VKN/AESA Minor Change-Moved to the external web
*D 2521072 06/25/08 NXR/PYRS Updated Logic block diagram, Changed the pin name from V_SS/144M and V_SS/288M
to NC/144M and NC/288M respectively in Pin Definition table, Changed JTAG ID
[31:29] from 001 to 000, Updated power up sequence waveform and its description,
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C
to +125°C” in the “Maximum Ratings “ on page 20, Added footnote #19 related to
I_DD, Changed Θ_JA spec from 16.2 to 16.3, Changed Θ_JC spec from 2.3 to 2.1.
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Document Number: 001-12559 Rev. *D
Revised June 25, 2008
Page 26 of 26
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
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