CYUSB3014_1107 Datasheet, PDF (25/38 Pages) Cypress Semiconductor – EZ-USB FX3 SuperSpeed USB Controller

PRELIMINARY
CYUSB3014
Asynchronous Slave FIFO Write Sequence
Description
■ FIFO address is driven and SLCS# is asserted
■ SLWR# is asserted. SLCS# must be asserted with SLWR# or
before SLWR# is asserted
■ Data must be present on the bus tWRS before the deasserting
edge of SLWR#
■ De-assertion of SLWR# causes the data to be written from the
data bus to the FIFO and then FIFO pointer is incremented
■ The FIFO flag is updated after the tWFLG from the de-asserting
edge of SLWR.
The same sequence of events is shown for a burst write.
Note that in the burst write mode, on SLWR# de-assertion, the
data is written to the FIFO and then the FIFO pointer is incre-
mented.
Table 11. Asynchronous Slave FIFO Parameters^[6]
Short Packet: A short packet can be committed to the USB host
by using the PKTEND#. The external device/processor should
be designed to assert the PKTEND# along with the last word of
data and SLWR# pulse corresponding to the last word. The
FIFOADDR lines have to be held constant during the PKTEND#
assertion.
Zero Length Packet: The external device/processor can signal a
Zero Length Packet (ZLP) to EZ-USB FX3, simply by asserting
PKTEND#, without asserting SLWR#. SLCS# and address must
be driven as shown in the above timing diagram.
FLAG Usage: The FLAG signals are monitored by the external
processor for flow control. FLAG signals are outputs from
EZ-USB FX3 that may be configured to show empty/full/partial
status for a dedicated address or the current address.
Parameter
tRDI
tRDh
tAS
tAH
tRFLG
tFLG
tRDO
tOE
tLZ
tOH
tWRI
tWRh
tWRS
tWRH
tWFLG
tPEI
tPEh
tWRPE
Description
SLRD# low
SLRD# high
Address to SLRD#/SLWR# setup time
SLRD#/SLWR#/PKTEND to address hold time
SLRD# to FLAGS output propagation delay
ADDR to FLAGS output propagation delay
SLRD# to data valid
OE# low to data valid
OE# low to data low-Z
SLOE# deassert data output hhold
SLWR# low
SLWR# high
Data to SLWR# setup time
SLWR# to Data Hold time
SLWR#/PKTEND to Flags output propagation delay
PKTEND low
PKTEND high
SLWR# deassert to PKTEND deassert
Min
Max
Units
20
–
ns
10
–
ns
7
–
ns
2
–
ns
–
35
ns
22.5
–
25
ns
–
25
ns
0
–
ns
–
22.5
ns
20
–
ns
10
–
ns
7
–
ns
2
–
ns
–
35
ns
7.5
–
ns
7.5
–
ns
0
–
Note
6. All parameters guaranteed by design and validated through characterization.
Document Number 001-52136 Rev. *I
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