CYIWOSC3000AA Datasheet, PDF (25/37 Pages) Cypress Semiconductor – 3.1 Megapixel CMOS Sensor

CYIWOSC3000AA
8.2.33 SYNCPOL(3A)
Bit #
Name
7 VSYNCPOL
6 HSYNCPOL
5 EXTRACLK
4 DATVAL
3 PCLKPOL
2 Reserved
1:0 MOD
DIR
Default
Function
RW
0
0 = VSYNC Active Low
1 = VSYNC Active High
RW
0
0 = HSYNC Active Low
1 = HSYNC Active High
RW
0
0 = PIXLCK only when pixels are present
1 = One extra PIXCLK when a row starts and ends
RW
0
0 = PIXCLK only clocks when HSYNC is inactive; HSYNC is a SYNC
pulse
1 = PIXCLK clocks continuously; HSYNC is a DATVAL pulse
RW
0
0 = PIXDATA transitions relative to the falling edge of PIXCLK
1 = PIXDATA transitions relative to the rising edge of PIXCLK
R
0
RW
00
00 = PIXCLK on valid data only
01 = PIXCLK on valid data and on ROWEND
02 = PIXCLK on valid data and when HSYNC inactive
03 = PIXCLK freeruns
The SYNCPOL register provides polarity control of the pixel data output pins. VSYNC will be high during Vertical Blanking time
when VSYNCPOL = 1. HSYNC will be high during the Horizontal Blanking time when HSYNCPOL = 1. The edge that PIXDATA
transitions on can be selected with the PCLKPOL bit. Normally PCLKPOL will want to be zero which sets the rising edge of
PIXCLK in the middle of a clock period where PIXDATA is stable. This will insure sufficient setup and hold times across a flex
cable to the back-end processor. If the back-end processor clocks data in on the falling edge of the clock or if there is a significant
amount of delay of PIXCLK, PCLKPOL may be programmed with a 1.
DATVAL = 1 changes the functionality of the HSYNC pin to be a “Data Valid” signal instead of a synchronization pulse. This mode
is normally used when MOD = 11 as PIXCLK is free-running and the back-end processor needs a signal to tell it when valid data
is present on the PIXDATA bus.
The MOD bits provide four different clocking modes that provide different options for clocking data into the back-end processor.
The simplest mode is MOD=00 where PIXCLK runs only when there is valid data on the PIXDATA bus. The problem with this
mode is that there are no clocks during HSYNC and VSYNC and many back-end processors need a few clocks during this time.
If the back-end processor needs to clock in HSYNC and VSYNC, use MOD = 01. This mode provides one extra clock each row
at the end of a row. This insures that HSYNC and VSYNC are sampled by the back-end processor. Note that this will increase
the size of the image by 1 pixel and this pixel must be ignored when doing image processing.
If PIXCLK needs to free-run during the syncs, use MOD = 10. In this mode it is assumed that the back-end processor knows that
it does not need to clock in the data when HSYNC is active. Note that PIXCLK will skip some pulses during the active portion of
a row if binning is enabled.
If PIXCLK needs to always free-run, then use MOD = 11. In this mode PIXCLK is the same as CLK except that it is delayed by
the internal clock buffers to match the output delay on the PIXDATA bus. In this mode DATVAL is normally set to 1 so that the
back-end processor knows which pixels have valid data or not. Some back-end processors are able to compute where the valid
pixels are in a row but care must be taken to properly align the data.
8.2.34 TSTPTN(3B)
Bit #
Name
2:0 TSTPTN
DIR
Default
Function
RW
00
000 = Test pattern disabled
001 = SMPTE colorbars
010 = Incrementing gradient in X
011 = Incrementing gradient in Y
1XX = Reserved
The TSTPTN register enables a test pattern to be output. There are three test patterns available. The standard SMPTE color bars
pattern, a 12-bit incrementing gradient in X and a 12-bit incrementing gradient in Y.
Document #: 38-19009 Rev. *E
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