CY7C1461AV33_08 Datasheet, PDF (25/32 Pages) Cypress Semiconductor – 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Switching Waveforms (continued)
Figure 3. NOP, STALL, and DESELECT Cycles^{[25, 26, 28]}
1
2
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS ^A1
A2
DQ
D(A1)
COMMAND _WRITE
READ
D(A1)
Q(A2)
3
4
A3
Q(A2)
STALL
READ
Q(A3)
5
6
7
8
9
10
A4
Q(A3)
WRITE
STALL
D(A4)
D(A4)
NOP
A5
tCHZ
Q(A5)
tDOH
READ DESELECT CONTINUE
Q(A5)
DESELECT
DON’T CARE
UNDEFINED
Note
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05356 Rev. *G
Page 25 of 32
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