CY7C1386D_11 Datasheet, PDF (25/36 Pages) Cypress Semiconductor – 18-Mbit (512 K x 36/1 M x 18) Pipelined DCD Sync SRAM

CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Waveforms
Figure 5. Read Cycle Timing ^[30]
tCYC
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
X
CE
ADV
OE
Data Out (DQ)
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
t _CO
t _OEHZ
Q(A1)
Single READ
tOEV
tCO
t _OELZ
tDOH
Q(A2) Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
BURST READ
t _CHZ
Q(A2) Q(A2 + 1)
Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note
30. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BW_X LOW.
Document Number: 38-05545 Rev. *H
Page 25 of 36
[+] Feedback