CYRF89435 Datasheet, PDF (23/40 Pages) Cypress Semiconductor – PRoC™ - CapSense®

AC Programming Specifications
Figure 6. AC Waveform
CYRF89435
SCLK (P1[1])
SDATA (P1[0])
T_RSCLK
T_FSCLK
T_SSCLK
T_HSCLK
T_DSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. AC Programming Specifications
Symbol
Description
Conditions
Min
Typ
Max Units
t_RSCLK
t_FSCLK
t_SSCLK
Rise time of SCLK
–
Fall time of SCLK
–
Data setup time to falling edge of –
SCLK
1
–
20
ns
1
–
20
ns
40
–
–
ns
t_HSCLK
Data hold time from falling edge –
of SCLK
40
–
–
ns
F_SCLK
t_ERASEB
t_WRITE
t_DSCLK3
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge
of SCLK
–
–
–
3.0  V_DD  3.6
0
–
8
MHz
–
–
18
ms
–
–
25
ms
–
–
85
ns
t_DSCLK2
Data out delay from falling edge 1.9  V_DD  3.0
of SCLK
–
–
130
ns
t_XRST3
External reset pulse width after Required to enter programming
300
–
power-up
mode when coming out of sleep
–
s
t_XRES
t_VDDWAIT
XRES pulse length
–
V_DD stable to wait-and-poll hold –
off
300
–
0.1
–
–
s
1
ms
t_VDDXRES
V_DD stable to XRES assertion –
delay
14.27
–
–
ms
t_POLL
t_ACQ
SDATA high pulse time
–
“Key window” time after a V_DD –
ramp acquire event, based on
256 ILO clocks.
0.01
–
200
ms
3.20
–
19.60
ms
t_XRESINI
“Key window” time after an
–
XRES event, based on 8 ILO
clocks
98
–
615
s
Document Number: 001-76581 Rev. *D
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