CY7C1380DV25 Datasheet, PDF (23/29 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Switching Waveforms (continued)
ZZ Mode Timing ^{[29, 30]}
CLK
ZZ
I _SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
t _ZZ
t _ZZI
I _DDZZ
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
t _ZZREC
High-Z
DON’T CARE
t _RZZI
DESELECT or READ Only
Notes:
29. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05546 Rev. *E
Page 23 of 29
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