CY7C12461KV18 Datasheet, PDF (23/29 Pages) Cypress Semiconductor – 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C12461KV18, CY7C12571KV18
CY7C12481KV18, CY7C12501KV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
C_IN
Input Capacitance
C_O
Output Capacitance
T_A = 25C, f = 1 MHz, V_DD = 1.8V, V_DDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
_JA
Thermal Resistance
(Junction to Ambient)
_JC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Figure 6. AC Test Loads and Waveforms
Max
4
4
165 FBGA
Package
13.7
3.73
Unit
pF
pF
Unit
°C/W
°C/W
V_REF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75V
Z₀ = 50
RQ =
250
V_REF
R_L = 50
V_REF = 0.75V
OUTPUT
Device
Under
Test ^ZQ
INCLUDING
JIG AND
SCOPE
V_REF = 0.75V
0.75V
R = 50
RQ =
250
(b)
5 pF ^0.25V
ALL INPUT PULSES^[21]
1.25V
0.75V
Slew Rate = 2 V/ns
Note
21.
Unless otherwise
levels of 0.25V to
noted,
1.25V,
test
and
conditions assume signal transition time of
output loading of the specified I_OL/I_OH and
2V/ns, timing reference levels
load capacitance shown in (a)
of
of
0A.C75TVe,sVt _{RLEoFad=s0a.7n5dVW,} RavQef=or2m5s0.,
V_DDQ
=
1.5V,
input
pulse
Document Number: 001-53194 Rev. *I
Page 23 of 29
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