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| CY7C1648KV18_12 Datasheet, PDF (22/30 Pages) Cypress Semiconductor – 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) | |||
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CY7C1648KV18
CY7C1650KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [26]
Description
VIH
Input high voltage
VIL
Input low voltage
Test Conditions
Min
VREF + 0.2
â0.24
Typ
Max
Unit
â VDDQ + 0.24 V
â
VREF â 0.2
V
Capacitance
Parameter [27]
Description
CIN
Input capacitance
CO
Output capacitance
Test Conditions
TA = 25 ï°C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
Max
Unit
4
pF
4
pF
Thermal Resistance
Parameter [27]
Description
ïJA
Thermal resistance
(junction to ambient)
ïJC
Thermal resistance
(junction to case)
Test Conditions
165-ball FBGA
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
12.55
2.49
°C/W
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75 V
Z0 = 50 ï
RQ =
250 ï
VREF
RL = 50 ï
VREF = 0.75 V
OUTPUT
Device
Under
Test ZQ
INCLUDING
JIG AND
SCOPE
VREF = 0.75 V
0.75 V
R = 50 ï
RQ =
250 ï
(b)
5 pF 0.25 V
ALL INPUT PULSES[28]
1.25 V
0.75 V
Slew Rate = 2 V/ns
Notes
26. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > ï0.3 V (Pulse width less than tCYC/2).
27. Tested initially and after any design or process change that may affect these parameters.
28.
Unless otherwise noted,
pulse levels of 0.25 V to
test conditions assume signal transition time of 2 V/ns, timing reference
1.25 V, and output loading of the specified IOL/IOH and load capacitance
lsehvoewlsnoifn0(.a7)5oVf ,FVigRuErFe
= 0.75
5.
V,
RQ
=
250
ï,
VDDQ
=
1.5
V,
input
Document Number: 001-44061 Rev. *H
Page 22 of 30
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