CY7C1516KV18 Datasheet, PDF (22/30 Pages) Cypress Semiconductor – 72-Mbit DDR-II SRAM 2-Word Burst Architecture

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
C_IN
Input Capacitance
C_O
Output Capacitance
Test Conditions
T_A = 25°C, f = 1 MHz, V_DD = 1.8V, V_DDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Θ_JA
Thermal Resistance
(Junction to Ambient)
Θ_JC Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
Figure 4. AC Test Loads and Waveforms
Max
2
3
165 FBGA
Package
13.7
3.73
Unit
pF
pF
Unit
°C/W
°C/W
V_REF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75V
Z₀ = 50Ω
RQ =
250Ω
V_REF
R_L = 50Ω
V_REF = 0.75V
OUTPUT
Device
Under
Test ^ZQ
INCLUDING
JIG AND
SCOPE
V_REF = 0.75V
0.75V
R = 50Ω
RQ =
250Ω
(b)
5 pF ^0.25V
[20]
ALL INPUT PULSES
1.25V
0.75V
Slew Rate = 2 V/ns
Note
20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V_REF = 0.75V, RQ = 250Ω, V_DDQ = 1.5V, input pulse
levels of 0.25V to 1.25V, and output loading of the specified I_OL/I_OH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-00437 Rev. *E
Page 22 of 30
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