CY7C1470BV33_13 Datasheet, PDF (22/34 Pages) Cypress Semiconductor – 72-Mbit (2 M x 36/4 M × 18/1 M x 72) Pipelined SRAM with NoBL™ Architecture

CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Boundary Scan Exit Order
(1 M × 72)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
209-ball ID
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
J2
L1
L2
M1
M2
N1
N2
P1
P2
R2
R1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-ball ID
T1
T2
U1
U2
V1
V2
W1
W2
T6
V3
V4
U4
W5
V6
W6
V5
U5
U6
W7
V7
U7
V8
V9
W11
W10
V11
V10
U11
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-ball ID
U10
T11
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
L10
P6
J11
J10
H11
H10
G11
G10
F11
F10
E10
E11
D11
D10
C11
C10
Bit #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
209-ball ID
B11
B10
A11
A10
A7
A5
A9
U8
A6
D6
K6
B6
K3
A8
B4
B3
C3
C4
C8
C9
B9
B8
A4
C6
B7
A3
Document Number: 001-15031 Rev. *K
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