CY7C1411JV18 Datasheet, PDF (22/26 Pages) Cypress Semiconductor – 36-Mbit QDR™-II SRAM 4-Word Burst Architecture

CY7C1411JV18, CY7C1426JV18
CY7C1413JV18, CY7C1415JV18
Switching Characteristics
Over the Operating Range ^[21]
Cypress Consortium
Parameter Parameter
Description
t_POWER
t_CYC
t_KHKH
t_KH
t_KHKL
t_KL
t_KLKH
t_KHKH
t_KHKH
t_KHCH
t_KHCH
Setup Times
V_DD(Typical) to the First Access ^[22]
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
300 MHz
Unit
Min Max
1
ms
3.3 8.4 ns
1.32 – ns
1.32 – ns
1.49 – ns
0 1.45 ns
t_SA
t_AVKH
t_SC
t_IVKH
t_SCDDR
t_IVKH
t_SD
t_DVKH
Hold Times
Address Setup to K Clock Rise
0.4 – ns
Control Setup to Clock (K, K) Rise (RPS, WPS)
0.4 – ns
Double Data Rate Control Setup to Clock (K, K) Rise (BWS₀, BWS₁, BWS₂, BWS₃) 0.3 – ns
D_[X:0] Setup to Clock (K/K) Rise
0.3 – ns
t_HA
t_KHAX
t_HC
t_KHIX
t_HCDDR t_KHIX
t_HD
t_KHDX
Output Times
Address Hold after Clock (K/K) Rise
0.4 – ns
Control Hold after Clock (K /K) Rise (RPS, WPS)
0.4 – ns
Double Data Rate Control Hold after Clock (K/K) Rise (BWS₀, BWS₁, BWS₂, BWS₃) 0.3 – ns
D_[X:0] Hold after Clock (K/K) Rise
0.3 – ns
t_CO
t_CHQV
t_DOH
t_CHQX
t_CCQO
t_CHCQV
t_CQOH
t_CHCQX
t_CQD
t_CQHQV
t_CQDOH t_CQHQX
t_CQH
t_CQHCQL
t_CQHCQH t_CQHCQH
t_CHZ
t_CHQZ
t_CLZ
t_CHQX1
DLL Timing
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH ^[23]
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge) ^[23]
Clock (C and C) Rise to High-Z (Active to High-Z) ^{[24, 25]}
Clock (C and C) Rise to Low-Z ^{[24, 25]}
– 0.45 ns
–0.45 – ns
– 0.45 ns
–0.45 – ns
0.27 ns
–0.27 – ns
1.24 – ns
1.24 – ns
– 0.45 ns
–0.45 – ns
t_{KC Var}
t_{KC lock}
t_{KC Reset}
t_{KC Var}
t_{KC lock}
t_{KC Reset}
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
– 0.20 ns
1024 – Cycles
30
ns
Notes
22. This part has a voltage regulator internally; t_POWER is the time that the power must be supplied above V_DD minimum initially before a read or write operation can be
initiated.
23. These parameters are extrapolated from the input timing parameters (t_KHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t_{KC Var}) ia already
included in the t_KHKH). These parameters are only guaranteed by design and are not tested in production
24. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
25. At any given voltage and temperature t_CHZ is less than t_CLZ and t_CHZ less than t_CO.
Document Number: 001-12557 Rev. *B
Page 22 of 26
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