CY7C1316BV18_06 Datasheet, PDF (22/28 Pages) Cypress Semiconductor – 18-Mbit DDR-II SRAM 2-Word Burst Architecture

CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Switching Characteristics Over the Operating Range^[22,23]
Cypress Consortium
Parameter Parameter
Description
300 MHz 278 MHz 250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_POWER
t_KHKH
VAc_DcDe(Tsysp[2i₄c_]al) to the first
1–1–1
1
1
ms
t_CYC
t_KHKL
K Clock and C Clock Cycle 3.30 5.25 3.60 5.25 4.0 6.3 5.0 7.9 6.0 8.4 ns
Time
t_KH
t_KLKH
Input Clock (K/K and C/C) 1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
HIGH
t_KL
t_KHKH
Input Clock (K/K and C/C) 1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns
LOW
t_KHKH
t_KHCH
K Clock Rise to K Clock 1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns
Rise and C to C Rise (rising
edge to rising edge)
t_KHCH
t_KHKH
K/K Clock Rise toC/C Clock 0.00 1.45 0.00 1.55 0.0 1.8 0.0 2.2 0.0 2.7 ns
Rise (rising edge to rising edge)
Set-up Times
t_SA
t_AVKH
Address Set-up to K Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
Rise
t_SC
t_IVKH
Control Set-up to K Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
Rise (LD, R/W)
t_SCDDR
t_IVKH
t_SD[25]
t_DVKH
Double Data Rate Control 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Set-up to Clock (K, K) Rise
(BWS₀, BWS₁, BWS₂,
BWS₃)
D_[X:0] Set-up to Clock
(K/K) Rise
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold Times
t_HA
t_KHAX
Address Hold after K Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
Rise
t_HC
t_KHIX
Control Hold after K Clock 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns
Rise (LD, R/W)
t_HCDDR
t_KHIX
t_HD
t_KHDX
Double Data Rate Control 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Hold after Clock (K, K) Rise
(BWS₀, BWS₁, BWS₂,
BWS₃)
D_[X:0] Hold after Clock
(K and K) Rise
0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns
Output Times
t_CO
t_CHQV
C/C Clock Rise (or K/K in
– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
single clock mode) to Data
Valid
t_DOH
t_CHQX
Data Output Hold after –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns
Output C/C Clock Rise
(Active to Active)
Notes:
23. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24. This part has a voltage regulator internally; t_POWER is the time that the power needs to be supplied above V_DD minimum initially before a read or write operation
can be initiated.
25. For DQ2 data signal on CY7C1916BV18 device, t_SD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document Number: 38-05621 Rev. *C
Page 22 of 28
[+] Feedback