CY28439-2 Datasheet, PDF (22/22 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

PRELIMINARY
CY28439-2
Document History Page
Document Title: CY28439-2 Clock Generator for Intel^ Grantsdale Chipset
Document Number: 38-07750
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
331153 See ECN RGL New data sheet
*A
378836 See ECN RGL Changed CPU Cycle-cycle jitter max from 50 to 80 ps
Changed CPU Rise/Fall Time min. from 175 to 130 ps
Changed SRC Rise/Fall Time min. from 175 to 130 ps
Changed DOT Rise/Fall Time min. from 175 to 130 ps
Changed DOT Cycle-cycle Jitter max from 150 to 250 ps
Changed USB,24_48M Rising/Falling Edge Rate max from 2 to 3 V/ns
Changed USB Cycle-cycle Jitter max from 200 to 350 ps
Changed USB High Time max from 10.04 to 10.9 ns
Changed USB Low Time max from 9.836 to 11.5 ns
Changed 24M High Time max from 20.07 to 22.7 ns
Changed 24M Low Time max from 19.67 to 22.6 ns
Revised Frequency Select table
*B
386202 See ECN RGL Minor Change: Mistype the Part no. in the ordering info.
Document #: 38-07750 Rev. *B
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