CYP15G0403DXB_07 Datasheet, PDF (21/45 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Transceiver

CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Table 9. Device Configuration and Control Latch Descriptions (continued)
Name
Signal Description
FRAMCHARA
FRAMCHARB
FRAMCHARC
FRAMCHARD
Framing Character Select. The initialization value of the FRAMCHARx latch = 1. FRAMCHARx is used to
select the character or portion of a character used for framing of each channel’s received data stream. When
FRAMCHARx = 1, the framer looks for either disparity of the K28.5 character. When FRAMCHARx = 0, the
framer looks for either disparity of the 8-bit Comma characters. The specific bit combinations of these framing
characters are listed in Table 6 on page 17.
DECMODEA
DECMODEB
DECMODEC
DECMODED
Receiver Decoder Mode Select. The initialization value of the DECMODEx latch = 1. DECMODEx selects
the Decoder Mode used for the associated channel. When DECMODEx = 1 and decoder is enabled, the
Cypress Decoding Mode is used. When DECMODEx = 0 and decoder is enabled, the Alternate Decoding
mode is used. When the decoder is enabled (DECBYPx = 1), the 10-bit transmission characters are decoded
using Table 15 on page 39 and Table 16 on page 43. The column used in the Special Characters Table 16 is
determined by the DECMODEx latch.
DECBYPA
DECBYPB
DECBYPC
DECBYPD
Receiver Decoder Bypass. The initialization value of the DECBYPx latch = 1. DECBYPx selects if the
Receiver Decoder is enabled or bypassed. When DECBYPx = 1, the decoder is enabled and the Decoder
Mode is selected by DECMODEx. When DECBYPx = 0, the decoder is bypassed and raw 10-bit characters
are passed through the receiver.
RXCKSELA
RXCKSELB
RXCKSELC
RXCKSELD
Receive Clock Select. The initialization value of the RXCKSELx latch = 1. RXCKSELx selects the receive
clock source used to transfer data to the Output Registers and the clock source for the RXCLK± output. When
RXCKSELx = 1, the associated Output Registers, are clocked by REFCLKx± at the associated RXCLKx±
output buffer. When RXCKSELx = 0, the associated Output Registers, are clocked by the Recovered Byte
clock at the associated RXCLKx± output buffer. These output clocks may operate at the character-rate or half
the character-rate as selected by RXRATEx.
RXRATEA
RXRATEB
RXRATEC
RXRATED
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select
the rate of the RXCLKx± clock output.
When RXRATEx = 1 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at half the character rate. Data for the associated receive channels should be
latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 and RXCKSELx = 0, the RXCLKx± clock outputs are complementary clocks that follow
the recovered clock operating at the character rate. Data for the associated receive channels should be latched
on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXRATEx = 1 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at half the character rate. Data for the
associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0 with RXCKSELx = 1 and REFCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks that follow the reference clock operating at the character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–.
When RXCKSELx = 1 and REFCLKx± is a half-rate clock, the value of RXRATEx is not interpreted and the
RXCLKx± clock outputs are complementary clocks that follow the reference clock operating at half the
character rate. Data for the associated receive channels should be latched alternately on the rising edge of
RXCLKx+ and RXCLKx–.
SDASEL1A[1:0]
SDASEL1B[1:0]
SDASEL1C[1:0]
SDASEL1D[1:0]
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0]
latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1± Primary
Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
SDASEL2A[1:0]
SDASEL2B[1:0]
SDASEL2C[1:0]
SDASEL2D[1:0]
Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the
SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2±
Secondary Differential Serial Data Inputs.
When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled
When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Document #: 38-02065 Rev. *F
Page 21 of 45
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