CY8CMBR2110_13 Datasheet, PDF (21/71 Pages) Cypress Semiconductor – CapSense® Express™ 10-Button Controller

CY8CMBR2110
Power Consumption and Operating Modes
CY8CMBR2110 can meet low-power requirements of
battery-powered applications. To design for the lowest operating
current, do the following:
■ Ground all unused CapSense inputs (CSx).
■ Minimize C_P using the design guidelines in Getting Started with
CapSense, section 3.7.1.
■ Reduce supply voltage (valid range: 1.71 V to 5.5 V).
■ Reduce the sensitivity of CSx buttons.
■ Configure the design to be optimized for power consumption.
■ Use ‘High’ Noise Immunity level only if needed.
■ Use a higher Button Scan Rate or Deep Sleep operating mode.
To know more about the steps to reduce power consumption,
refer to section 5 in the CY8CMBR2110 Design Guide.
Low-Power Sleep Mode
The following flowchart describes the Low-Power Sleep mode
operation.
■ The Button Scan Rate is equal to the sum of the time the device
scans and sleeps.
■ The register settings define a Button Scan Rate offset.
■ The offset is added to a constant to get the Button Scan Rate.
■ The constant is given in Table 7.
■ The range of scan rate is 25 to 561 ms.
Figure 36. Low Power Sleep Mode Operation
Scan all buttons with
Button Scan Rate constant
No
NO button touched for
15 secs?
Yes
Yes
ScSacnaanllablul tbtounttsonwsithwuithseBr udtetofined
But^Sto^cn^aSⁿc^Ra^an^tR^e ate
No
Is any button
Active?
Table 7. Button Scan Rate Constant
Button Count
≤5
>5
Button Scan Rate Constant
Response Time Optimized Design
Power Consumption Optimized Design
Noise Immunity Level
“Normal”
Noise Immunity Level
“High”
Noise Immunity Level
“Normal”
Noise Immunity Level
“High”
25 ms
35 ms
35 ms
55 ms
35 ms
55 ms
35 ms
55 ms
Deep Sleep Mode
■ To enable the Deep Sleep mode, connect the Attention/Sleep
line to the host as shown in Figure 37; the host should perform
the following steps:
❐ Pull the Attention/Sleep line low
❐ Set the Deep Sleep bit in the Host_Mode register (in Oper-
ating Mode) high
❐ Wait for 50 ms
❐ Pull the Attention/Sleep line high
Figure 37. Attention/Sleep pin Connection to Enable Deep
Sleep Mode
Attention/Sleep
Digital I/O pin
■ In Deep Sleep mode, all blocks are turned off and the device
power consumption is 0.1 µA.
■ There is no CapSense scanning in Deep Sleep mode.
■ After the device enters Deep Sleep mode, the ‘Deep Sleep’ bit
is automatically cleared.
■ The Attention/Sleep line should be pulled low for the device to
wake up from Deep Sleep.
■ When device comes out of Deep Sleep mode, the CapSense
system is re-initialized. The typical time for re-initialization is
20 ms (Normal Noise Immunity level) or 50 ms (High Noise
Immunity level). Any button touch within this time is not
reported.
■ The Deep Sleep bit cannot be set by EZ-Click Customizer Tool
and must be set by an external I²C communication to the
device.
CY8CMBR2110
Host Controller
Document Number: 001-74494 Rev. *B
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