CY8C24223A_06 Datasheet, PDF (21/33 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C24x23A Automotive Data Sheet
3. Electrical Specifications
3.4 AC Electrical Characteristics
3.4.1 AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 3-13. AC Chip-Level Specifications
Symbol
F_IMO24
F_CPU1
F_48M
F_24M
F_32K1
F_32K2
Description
Internal Main Oscillator Frequency for 24 MHz
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
Min
22.95
0.09
–
0
15
–
Typ
24
12
–
24
32
32.768
Max
24.96
12.48
–
24.96^a
64
–
F_PLL
PLL Frequency
–
Jitter24M2 24 MHz Period Jitter (PLL)
–
T_PLLSLEW PLL Lock Time
0.5
T_PLLSLEWS- PLL Lock Time for Low Gain Setting
0.5
LOW
T_OS
External Crystal Oscillator Startup to 1%
–
T_OSACC
External Crystal Oscillator Startup to 100 ppm
–
Jitter32k
32 kHz Period Jitter
–
T_XRST
External Reset Pulse Width
10
DC24M
24 MHz Duty Cycle
40
Step24M 24 MHz Trim Step Size
–
Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak
–
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared
–
F_MAX
Maximum frequency of signal on row input or row output. –
T_RAMP
Supply Ramp Time
0
23.986 –
–
800
–
10
–
50
1700
2800
100
–
50
50
300
–
–
–
2620
3800
–
60
–
600
12.48
–
a. See the individual user module data sheets for information on maximum frequencies for user modules.
Units
MHz
MHz
MHz
MHz
kHz
kHz
MHz
ps
ms
ms
Notes
Trimmed. Utilizing factory trim values.
Not allowed.
Accuracy is capacitor and crystal dependent.
50% duty cycle.
Is a multiple (x732) of crystal frequency.
ms
ms
ns
µs
%
kHz
ps
ps
MHz
µs
PLL
Enable
F_PLL
T_PLLSLEW
PLL
Gain ⁰
Figure 3-2. PLL Lock Timing Diagram
24 MHz
October 9, 2006
Document No. 38-12029 Rev. *C
21
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