CY7C2561KV18 Datasheet, PDF (21/29 Pages) Cypress Semiconductor – 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture

PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on V_DD Relative to GND ........–0.5V to +2.9V
Supply Voltage on V_DDQ Relative to GND.......–0.5V to +V_DD
DC Applied to Outputs in High-Z ........ –0.5V to V_DDQ + 0.3V
DC Input Voltage ^[15].............................. –0.5V to V_DD + 0.3V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (T_A)
0°C to +70°C
–40°C to +85°C
V_DD ^[19]
1.8 ± 0.1V
V_DDQ ^[19]
1.4V to
V_DD
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range ^[16]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
V_DD
V_DDQ
V_OH
V_OL
V_OH(LOW)
V_OL(LOW)
V_IH
V_IL
I_X
I_OZ
V_REF
I_DD ^[23]
Power Supply Voltage
1.7
1.8
1.9
V
IO Supply Voltage
Output HIGH Voltage
Note 20
Output LOW Voltage
Note 21
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
I_OH = −0.1 mA, Nominal Impedance
I_OL = 0.1 mA, Nominal Impedance
Input LOW Voltage
Input Leakage Current
GND ≤ V_I ≤ V_DDQ
Output Leakage Current GND ≤ V_I ≤ V_DDQ, Output Disabled
Input Reference Voltage ^[22] Typical Value = 0.75V
1.4
1.5
V_DD
V
V_DDQ/2 – 0.12
V_DDQ/2 + 0.12 V
V_DDQ/2 – 0.12
V_DDQ/2 + 0.12 V
V_DDQ – 0.2
V_DDQ
V
V_SS
0.2
V
V_REF + 0.1
V_DDQ + 0.15 V
–0.15
V_REF – 0.1
V
−2
2
μA
−2
2
μA
0.68
0.75
0.95
V
V_DD Operating Supply
V_DD = Max,
I_OUT = 0 mA,
f = f_MAX = 1/t_CYC
550 MHz (x8)
(x9)
(x18)
900
mA
900
920
(x36)
1310
500 MHz (x8)
830
mA
(x9)
830
(x18)
850
(x36)
1210
450 MHz (x8)
760
mA
(x9)
760
(x18)
780
(x36)
1100
400 MHz (x8)
690
mA
(x9)
690
(x18)
710
(x36)
1000
Notes
19.
20.
Power
Output
up: Assumes a
are impedance
linear ramp from
controlled. I_OH =
0_−V(Vto_DDV_{QD/D2)(m/(RinQ) /w5)ithfoinr}
200 ms. During this
values of 175 ohms
time V_IH <
<= RQ <=
V_DD and V_DDQ
350 ohms.
<
V_DD.
21. Output are impedance controlled. I_OL = (V_DDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
22. V_REF (min) = 0.68V or 0.46V_DDQ, whichever is larger, V_REF (max) = 0.95V or 0.54V_DDQ, whichever is smaller.
23. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15887 Rev. *E
Page 21 of 29
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