CY7C1386D_07 Datasheet, PDF (21/30 Pages) Cypress Semiconductor – 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM

CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
Switching Waveforms
Read Cycle Timing ^[26]
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
X
CE
ADV
OE
Data Out (DQ)
tCYC
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
t _CO
t _OEHZ
Q(A1)
Single READ
tOEV
tCO
t _OELZ
tDOH
Q(A2) Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
BURST READ
t _CHZ
Q(A2) Q(A2 + 1)
Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note
26. On this diagram, when CE is LOW, CE₁ is LOW, CE₂ is HIGH and CE₃ is LOW. When CE is HIGH: CE₁ is HIGH or CE₂ is LOW or CE₃ is HIGH.
Document Number: 38-05545 Rev. *E
Page 21 of 30
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