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| CY7C0430BV Datasheet, PDF (21/37 Pages) Cypress Semiconductor – 10 Gb/s 3.3V QuadPort DSE Family | |||
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Switching Waveforms (continued)
Counter Interrupt [31, 43, 44, 45]
CLK
tCYC2
tCH2
tCL2
EXTERNAL
ADDRESS
007Fh
tSMLD
MKLD
CNTLD
xx7Dh
tHMLD
tSCLD
CNTINC
tHCLD
tSCINC
tHCINC
COUNTER
INTERNAL
ADDRESS
An
xx7Dh
CNTINT
Mailbox Interrupt Timing[46, 47, 48, 49, 50]
CLKP1
tCYC2
tCH2
tCL2
PORT-1
ADDRESS
INTP2
tSA tHA
FFFE
An
tSINT
CLKP2
tCYC2
tCH2
tCL2
xx7Eh
xx7Fh
tSCINT
An+1
tRINT
An+2
CY7C0430BV
CY7C04312BV
CY7C04314BV
xx00h
xx00h
tRCINT
An+3
PORT-2
ADDRESS
tSA tHA
Am
Am+1
FFFE
Am+3
Am+4
Notes:
43. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.
44. CNTINT is always driven.
45. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The âxâ is âDonât Care.â
46. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.
47. Address âFFFEâ is the mailbox location for Port 2.
48. Port 1 is configured for Write operation, and Port 2 is configured for Read operation.
49. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.
50. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.
Document #: 38-06027 Rev. *A
Page 21 of 37
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