CY7C2663KV18 Datasheet, PDF(20/31 Page) Cypress Semiconductor – 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C2663KV18 Datasheet, PDF (20/31 Pages) Cypress Semiconductor – 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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CY7C2663KV18, CY7C2665KV18

Power-Up Sequence in QDR II+ SRAM

QDR II+ SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

Power-Up Sequence

â Apply power and drive DOFF either high or low (All other inputs

can be high or low).

â Apply VDD before VDDQ.

â Apply VDDQ before VREF or at the same time as VREF.

â Drive DOFF high.

â Provide stable DOFF (high), power and clock (K, K) for 20 ïs

to lock the PLL

PLL Constraints

â PLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as tKC Var.

â The PLL functions at frequencies down to 120 MHz.

â If the input clock is unstable and the PLL is enabled, then the

PLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide 20 ïs of stable clock to

relock to the desired clock frequency.

Figure 4. Power-Up Waveforms

VDD/ VDDQ

DOFF

Unstable Clock

> 20Î¼s Stable clock

Clock Start (Clock Starts after VDD / VDDQ Stable)

VDD / VDDQ Stable (< +/- 0.1V DC per 50ns )

Fix HIGH (or tie to VDDQ)

Start Normal

Operation

Document Number: 001-44141 Rev. *K

Page 20 of 31

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