CY7C1141V18 Datasheet, PDF (20/28 Pages) Cypress Semiconductor – 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Power Up Sequence in QDR-II+ SRAM
During Power Up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. QDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations.
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t_{KC Var}.
■ The DLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ Apply power with DOFF tied HIGH (all other inputs can be HIGH
or LOW)
— Apply V_DD before V_DDQ
— Apply V_DDQ before V_REF or at the same time as V_REF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Waveforms
Figure 5. Power Up Waveforms
K
K
VDD/VDDQ
DOFF
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after VDD/VDDQ is Stable)
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to VDDQ)
Start Normal
Operation
Document Number: 001-06583 Rev. *C
Page 20 of 28
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