W40S11-23G Datasheet, PDF (2/11 Pages) Cypress Semiconductor – Clock Buffer/Driver

W40S11-23
Pin Definitions
Pin
Pin Name
No.
SDRAM0:12
2, 3, 6, 7, 10,
11, 18, 19,
22, 23, 26,
27, 12
BUF_IN
9
SDATA
14
SCLOCK
15
VDD
GND
1, 5, 13, 20,
24, 28
4, 8, 16, 17,
21, 25
Pin
Type
O
I
I/O
I
P
G
Pin Description
SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to
within ± 250 ps of each other.
Clock Input: This clock input has an input threshold voltage of 1.5V (typ).
SMBus Data Input: Data should be presented to this input as described in the SMBus
section of this data sheet. Internal 250-kΩ pull-up resistor.
SMBus Clock Input: The SMBus data clock should be presented to this input as
described in the SMBus section of this data sheet. Internal 250-kΩ pull-up resistor.
Power Connection: Power supply for core logic and output buffers. Connected to 3.3V
supply.
Ground Connection: Connect all ground pins to the common system ground plane.
Functional Description
Output Drivers
The W40S11-23 output buffers are CMOS type which deliver
a rail-to-rail (GND to V_DD) output voltage swing into a nominal
Table 1. Byte Writing Sequence
capacitive load. Thus output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15Ω.
Operation
Data is written to the W40S11-23 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W40S11-23 to accept the bits in Data Bytes 0–6 for in-
ternal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W40S11-23
is 11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Don’t Care
Unused by the W40S11-23, bit values are ignored (Don’t Care). This byte
Code
must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the W40S11-23, bit values are ignored (Don’t Care). This byte
must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
4
Data Byte 0
Refer to Table 2 The data bits in these bytes set internal W40S11-23 registers that control
5
Data Byte 1
device operation. The data bits are only accepted when the Address Byte
bit sequence is 11010010, as noted above. For description of bit control
6
Data Byte 2
functions refer to Table 2.
7
Data Byte 3
Don’t Care
Refer to Cypress Frequency Timing Generators.
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
2
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