STK11C68-5 Datasheet, PDF (2/15 Pages) Cypress Semiconductor – 64 Kbit (8K x 8) SoftStore nvSRAM

Pinouts
Figure 1. Pin Diagram - 28-Pin DIP
1&
$_
$_
$_
$_
$_
$_
$_
$_
$_
'4_
'4_
'4_
9₆₆














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9_&&
:(
1&
$_
$
$ _
2(
$ _
&(
'4 
'4 _
'4 _
'4_
'4_
STK11C68-5 (SMD5962-92324)
Figure 2. Pin Diagram - 28-Pin LLC
Pin Definitions
Pin Name Alt
A₀–A₁₂
DQ₀-DQ₇
WE
W
CE
E
OE
G
V_SS
V_CC
I/O Type
Description
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Input/Output Bidirectional Data I/O Lines. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 001-51001 Rev. *A
Page 2 of 15
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