PALCE22V10_96 Datasheet, PDF (2/13 Pages) Cypress Semiconductor – Flash Erasable, Reprogrammable CMOS PAL® Device

PALCE22V10
Selection Guide
Generic Part Number
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
t_PD ns
Com’l Mil/Ind
5
7.5
10
10
15
15
25
25
t_S ns
Com’l Mil/Ind
3
5
6
6
10
10
15
15
t_CO ns
Com’l Mil/Ind
4
5
7
7
8
8
15
15
I_CC mA
Com’l Mil/Ind
130
130
90
150
90
120
90
120
Functional Description (continued)
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through “array” configurable “output enable” for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Configuration Table
Registered/Combinatorial
C₁
C₀
0
0
Configuration
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
Document #: 38-03027 Rev. **
Page 2 of 13