CY7C9537B Datasheet, PDF (2/43 Pages) Cypress Semiconductor – OC-48/STM-16 Framer-POSIC2G

CONFIDENTIAL
CY7C9537B
LAN &
CBR
W AN
E /O
D ata Link
CY7C9537B
CYS25G0101DX
D evice
U TO P IA
PO S-PHY
or
HBST
PO SIC
T ra n s c e ive r
ATM SAR
O /E
O C -48
CPU
Figure 1. POSIC2G System Application Diagram
POSIC2G Logic Block Diagram
TXCLKI TXCLKOUT
SONETTX_PAROUT
TXD[31:0]
TXFRAME_PULSE
POHSDIN
TOHSDIN
TE1STROBE
TE2STROBE
TX SONET Line Interface
TranTsFemxratitmSeOr NET _SONET
Transmit SONET Framing
Overhead Processor Bypass
Pointer Processor
TX
ATM
Encapsulator
TX
HDLC
Encapsulator
TX
Generic
Protocol
Encapsulator
RXD[31:0]
LFI
I
RXFRAME
_PULSE
RXCLKs
RXCLK
RX SONET Line Interface
RecReeivceive SONET
SONET SOReNeEcDeiev-eFSraOmNeEr _T
FBryapmaisnsgOvaTedrhePO_rv_oe_cr_eh_se_sa_od_r
InsPeortinoter Processor
n
SONETRXPARIN
Clk2MHz
Clk16MHz
POHSDOUT
RPOHSTART
TPOHSTART
RE1STROBE
RE2STROBE
TOHSDOUR
RX
RX
ATM
HDLC
Decapsulator ^Decapsulator
RX
Generic
Protocol
Decapsulator
Programmable
Frame
Tagging
Engine
TCK
TRST
TDI
TMS
TDO
JTAG
Interface
General
Pins
Transmit UTOPIA/SPI-3
Interface
RST_n
SYSCLK
RSTOUT_n
CLKOUT
TEST[2:0]
MISC[15:0]
POSIC_OEN
SCAN_ENA
TFCLK
TERR
TDAT[31:0]
TPRTY
TADD[3:0]
TMOD[1:0]
TSOP
TEOP
STPA
PTCA
TENB
TSX
DTCA[3:0]
CPU
Interface
Receive UTOPIA/SPI-3
Interface
CpuClk
CpuTs_n/CpuAds_n
CpuSel
CpuBlast_n
CpuTa_n
ChipSel
CpuInt
CpuClkFail
CpuWrRd
CpuAD[31:0]
Mode
RVAL
RENB
RFCLK
RDAT[31:0]
RADD[70]
RMOD[1:0]
RPRTY
RERR
REOR
RSOP
RCA
RSX
Document #: 38-02079 Rev. *F
Page 2 of 43