CY7C1470V25_06 Datasheet, PDF (2/28 Pages) Cypress Semiconductor – 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture

CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram-CY7C1472V25 (4M x 18)
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
O
U
T
S
E
N
P
U
T
WRITE
DRIVERS
S
MEMORY
E
ARRAY
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1474V25 (1M x 72)
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 _D1
Q1 ^A1'
A0 _D0 BURST _Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
O
U
T
S
E
N
P
U
T
WRITE
DRIVERS
S
MEMORY
E
ARRAY
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
450
120
200 MHz
3.0
450
120
167 MHz
Unit
3.4
ns
400
mA
120
mA
Document #: 38-05290 Rev. *I
Page 2 of 28
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