CY7C1444AV33_12 Datasheet, PDF (2/23 Pages) Cypress Semiconductor – 36-Mbit (1 M × 36) Pipelined DCD Sync SRAM

CY7C1444AV33
Logic Block Diagram – CY7C1444AV33
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQD,DQPD
BYTE
WRITE REGISTER
DQc,DQPC
BYTE
WRITE REGISTER
DQB,DQPB
BYTE
WRITE REGISTER
DQA,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD,DQPD
BYTE
WRITE DRIVER
DQc,DQPC
BYTE
WRITE DRIVER
DQB,DQPB
BYTE
WRITE DRIVER
DQA,DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
OUTPUT
SENSE
AMPS
REGISTERS
OUTPUT
BUFFERS
DQs
E
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 38-05352 Rev. *J
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