CY7C09269V Datasheet, PDF (2/19 Pages) Cypress Semiconductor – 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

CY7C09269V/79V/89V
CY7C09369V/79V/89V
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided, permit-
ting independent, simultaneous access for reads and writes to
any location in memory.^[6] Registers on control, address, and
data lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid t_CD2 = 6.5 ns^{[1, 2]} (pipelined). Flow-through
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available t_CD1 = 18 ns after the address is clocked into the
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW
to HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
Pin Configurations
A HIGH on CE₀ or LOW on CE₁ for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE₀ LOW and CE₁
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH tran-
sition of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter Reset (CNTRST) is
used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
100-Pin TQFP (Top View)
A9L
A10L
A11L
A12L
A13L
[7] _A14L
[8] _A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
[9] _FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
CY7C09289V (64K x 16)
65
12
64
13
CY7C09279V (32K x 16)
63
14
62
15
CY7C09269V (16K x 16)
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R
A10R
A11R
A12R
A13R
A14R ^[7]
A15R ^[8]
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER ^[9]
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
Notes:
6. When writing simultaneously to the same location, the final value cannot be guaranteed.
7. This pin is NC for CY7C09269V.
8. This pin is NC for CY7C09269V and CY7C09279V.
9. For CY7C09269V and CY7C09279V, pin #18 connected to V_CC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5V x16 flow-through device.
Document #: 38-06056 Rev. **
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