CY5057 Datasheet, PDF (2/10 Pages) Cypress Semiconductor – High-Frequency Flash Programmable PLL Die with Spread Spectrum

CY5057
Block Diagram
XIN
XOUT
Crystal Osc
with 8-bit
Cap Array
SSON#
Spread
Spectrum
7-bit
÷Q
10-bit
÷P
100- to
400-MHz
PLL
7-bit
Output
Divider
Block
OUT
PD#/OE
Flash Configuration/
Spread Spectrum Storage
Die Pad Summary
Pad coordinates are referenced from the center of the die (X = 0, Y = 0)
Table 1. Die Pad Summary
Name
V_DD
V_SS
XIN
XOUT
PD#/OE
V_PP
SDA
SSON#
SCL
OUT
NC
Die Pad
Description
1,2 Power supply.
6,7 Ground.
4 Crystal gate pin.
3 Crystal drain pin.
5 Flash programmable to function as power down or output enable in
normal operating mode. Weak pull up is enabled by default.
Super voltage when going into programming mode.
Data pin when going into and when in programming mode.
10 Active low spread spectrum control. Asserting LOW turns the
internal modulation waveform on. Strong pull down is enabled by
default. Pull down is disabled in power down mode.
Clock pin in programming mode. Must be double bonded to the OUT
pad for pinouts not using the SSON# function. There is an internal
pull down resistor on this pad.
9 Clock output. There is an internal pull down resistor on this pad.
Weak pull down is enabled by default. Default output is from the
reference.
8 No connect pin (do not connect this pad).
X Coordinate
Y Coordinate
–843.612
597.849, 427.266
883.743, 887.355 –563.304, –369.957
–843.612
–1.806
–843.612
236.565
–843.612
–424.662
834.183
589.848
834.183
834.183
462.840
335.832
Document Number: 38-07363 Rev. *C
Page 2 of 10
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