CY28442 Datasheet, PDF (2/22 Pages) Cypress Semiconductor – Clock Generator for Intel Alviso Chipset

ADVANCE INFORMATION
CY28442
Pin Definitions
Pin No.
1
2
33,32
Name
VDD_REF
VSS_REF
CLKREQA#/SRCT6,
CLKREQB#,SRCC6
7
6
3,4,5
8
9
10
VDD_PCI
VSS_PCI
PCI
ITP_EN/PCIF0
PCIF1/96_100_SEL
VTT_PWRGD#/PD
11
12
13
14,15
16
VDD_48
FS_A/48_M0
VSS_48
DOT96T, DOT96C
FS_B/TEST_MODE
17,18
96_100_SSC
19,20,22,23, SRCT/C
24,25,30,31
21,28
VDD_SRC
34
VDD_SRC_ITP
26,27
SRC4_SATAT,
SRC4_SATAC
29
VSS_SRC
36,35
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
37
VDDA
38
VSSA
39
IREF
42
44,43,41,40
45
46
47
VDD_CPU
CPUT/C
VSS_CPU
SCLK
SDATA
Type
Description
PWR 3.3V power supply for outputs.
GND Ground for outputs.
I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active low) or 100 MHz
Serial Reference Clock.
Selectable through
CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to
enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte
8.
PWR 3.3V power supply for outputs.
GND Ground for outputs.
O, SE 33-MHz clock
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33 MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100MHz, 0 = 96MHz
I, PU
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for
asserting power down (active high).
PWR 3.3V power supply for outputs.
I/O 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND Ground for outputs.
O, DIF Fixed 96-MHz clock output.
I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O,DIF Differential 96/100 MHz SS clock for flat-panel display
O, DIF 100MHz Differential serial reference clocks.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
O, DIF Differential serial reference clock. Recommended output for SATA.
GND Ground for outputs.
O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
PWR 3.3V power supply for PLL.
GND Ground for PLL.
I A precision resistor is attached to this pin, which is connected to the internal
current reference.
PWR 3.3V power supply for outputs.
O, DIF Differential CPU clock outputs.
GND Ground for outputs.
I SMBus-compatible SCLOCK.
I/O SMBus-compatible SDATA.
Document #: 38-07680 Rev. **
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