CY28442-2_05 Datasheet, PDF (2/21 Pages) Cypress Semiconductor – Clock Generator for Intel Alviso Chipset

CY28442-2
Pin Definitions
Pin No.
Name
Type
Description
1
VDD_REF
PWR 3.3V power supply for output
2
VSS_REF
GND Ground for outputs.
33,32
CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz
CLKREQB#,SRCC6
Serial Reference Clock.
Selectable through CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB#
defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS
register Byte 8.
7
VDD_PCI
PWR 3.3V power supply for outputs.
6
VSS_PCI
GND Ground for outputs.
3,4,5
PCI
O, SE 33-MHz clock
8
ITP_EN/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1/96_100_SEL I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100 MHz, 0 = 96 MHz
10
VTT_PWRGD#/PD I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for
asserting power-down (active HIGH).
11
VDD_48
PWR 3.3V power supply for outputs.
12
FS_A/48_M0
I/O 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
13
VSS_48
GND Ground for outputs.
14,15
DOT96T, DOT96C O, DIF Fixed 96-MHz clock output.
16
FS_B/TEST_MODE I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
17,18
96_100_SSC
O,DIF Differential 96-/100-MHz SS clock for flat-panel display
19,20,22,23, SRCT/C
24,25,30,31
O, DIF 100-MHz Differential serial reference clocks.
21,28
VDD_SRC
PWR 3.3V power supply for outputs.
34
VDD_SRC_ITP
PWR 3.3V power supply for outputs.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
29
VSS_SRC
GND Ground for outputs.
36,35
CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC7
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
37
VDDA
PWR 3.3V power supply for PLL.
38
VSSA
GND Ground for PLL.
39
IREF
I A precision resistor is attached to this pin, which is connected to the internal
current reference.
42
VDD_CPU
PWR 3.3V power supply for outputs.
44,43,41,40 CPUT/C
O, DIF Differential CPU clock outputs.
45
VSS_CPU
GND Ground for outputs.
46
SCLK
I SMBus-compatible SCLOCK.
47
SDATA
I/O SMBus-compatible SDATA.
Document #: 38-07691 Rev. *B
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