CY25702 Datasheet, PDF (2/7 Pages) Cypress Semiconductor – Programmable High-Frequency Crystal Oscillator (XO)

CY25702
Pin Definition
Pin
1
Name
OE/PD#
2
VSS
3
CLK
4
VDD
Description
Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.
Power supply ground.
Clock output.
3.3V or 5.0V power supply.
Functional Description
The CY25702 is a Crystal Oscillator (XO).
The device uses a Cypress proprietary PLL to synthesize the
frequency of the embedded input crystal.
Table 1. Programming Data Requirement
The CY25702 uses a programmable configuration memory
array to synthesize output frequency.
The frequency CLK output can be programmed from 10–125
MHz.
The CY25702 is available in a 4-pin plastic SMD packages
with operating temperature range of –20 to 70°C.
Pin Function
Pin Name
Pin#
Units
Program Value
Output Frequency
CLK
3
MHz
ENTER DATA
Output Enable/Power Down
OE/PD#
1
N/A
ENTER DATA
Power Supply
VDD
4
V
ENTER DATA
Programming Description
Field/Factory-Programmable CY25702
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Output Frequency, CLK Output (CLK, pin 3)
The frequency at the CLK output is produced by synthesizing
the embedded crystal oscillator frequency input. The range of
Operating Conditions
synthesized clock is from 1–125MHz when VDD= 5V and
1–90MHz when VDD = 3.3V.
Output Enable or Power Down (OE/PD#, pin 1)
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
Absolute Maximum Rating
Supply Voltage (VDD).....................................–0.5V to +7.0V
DC Input Voltage ................................... –0.5V to V_DD + 0.5V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Parameter
V_DD1
V_DD2
T_A
C_LOAD
F_CLK1
F_CLK2
T_PU
Description
Supply Voltage Range
Supply Voltage Range
Ambient Temperature
Max. Load Capacitance @ pin 3
CLK output frequency, C_LOAD = 15 pF, VDD = 5.0V
CLK output frequency, C_LOAD = 15 pF, , VDD = 3.3V
Power-up time for VDD to reach minimum specified
voltage (power ramp must be monotonic)
Min.
3.00
4.50
–20
–
1.0
1.0
0.05
Typ.
3.30
5.00
–
–
–
–
–
Max.
3.60
5.50
70
15
125
90
500
Unit
V
V
°C
pF
MHz
MHz
ms
DC Electrical Characteristics
Parameter
Description
V_OH1
V_OL1
High Output Voltage
Low Output Voltage
Condition
V_DD = 5.0V, I_OH = –16mA
V_DD= 5.0V , I_OL= 16mA
Min.
V_DD-0.4
–
Typ.
–
–
Max. Unit
–
V
0.4 V
Document #: 38-07721 Rev. **
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