CY2509_09 Datasheet, PDF (2/6 Pages) Cypress Semiconductor – Spread Aware Ten/Eleven Output Zero Delay Buffer

CY2509/10
Pin Definitions
Pin
Name
Pin No.
(2509)
CLK
24
FBIN
13
Q0:8
Q9
3, 4, 5, 8,
9, 16, 17,
20, 21
n/a
FBOUT
12
AVDD
23
AGND
VDD
GND
OE
1
2, 10, 15,
22
6, 7, 18,
19
n/a
OE0:4
11
OE5:8
14
Pin No.
(2510)
24
13
3, 4, 5, 8,
9, 15, 16,
17, 20
21
12
23
1
2, 10, 14,
22
6, 7, 18,
19
11
n/a
n/a
Pin
Type
I
I
O
O
O
P
G
P
G
I
I
I
Pin Description
Reference Input: Output signals Q0:9 will be synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (typically FBOUT)
to ensure proper functionality. If the trace between FBIN and FBOUT is equal in
length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the CLK signal input.
Integrated Series Resistor Outputs: The frequency and phase of the signals
provided by these pins will be equal to the reference signal if properly laid out.
Each output has a 25Ω series damping resistor integrated.
Integrated Series Resistor Output: The frequency and phase of the signal
provided by this pin will be equal to the reference signal if properly laid out. This
output has a 25Ω series damping resistor integrated.
Feedback Output: This output has a 25Ω series resistor integrated on chip.
Typically it is connected directly to the FBIN input with a trace equal in length to
the traces between outputs Q0:9 and the destination points of these output
signals.
Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce
noise for optimal jitter performance.
Analog Ground Connection: Connect to common system ground plane.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
Ground Connections: Connect to common system ground plane.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought
to GND (LOW, 0) all outputs are disabled to a LOW state.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought
to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When brought
to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Overview
The CY2509/10 is a PLL-based clock driver designed for use
in dual inline memory modules. The clock driver has output
frequencies of up to 133 MHz and output to output skews of
less than 250 ps. The CY2509/10 provides minimum cycle-to-
cycle and long-term jitter, which is of significant importance to
meet the tight input-to-input skew budget in DIMM applica-
tions.
The current generation of 256- and 512-megabyte memory
modules needs to support 100-MHz clocking speeds.
Especially for cards configured in 16x4 or 8x8 format, the clock
signal provided from the motherboard is generally not strong
enough to meet all the requirements of the memory and logic
on the DIMM. The CY2509/10 takes in the signal from the
motherboard and buffers out clock signals with enough drive
to support all the DIMM board clocking needs. The CY2509/10
is also designed to meet the needs of new PC133 SDRAM
designs, operating to 133 MHz.
The CY2509/10 was specifically designed to accept SSFTG
signals currently being used in motherboard designs to reduce
EMI. Zero delay buffers which are not designed to pass this
feature through may cause skewing failures.
Output enable pins allow for shutdown of output when they are
not being used. This reduces EMI and power consumption.
Document #: 38-07230 Rev. *C
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