CY22150_09 Datasheet, PDF (2/16 Pages) Cypress Semiconductor – One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

CY22150
Pin Configuration
Table 1. Pin Definitions
Name
XIN
Number
1
VDD
2
AVDD
3
SDAT
4
AVSS
5
VSSL
6
LCLK1
7
LCLK2
8
LCLK3
9
SCLK
10
VDDL
11
LCLK4
12
VSS
13
CLK5
14
CLK6
15
XOUT^[1]
16
Figure 1. 16-Pin TSSOP
XIN 1
VDD 2
AVDD 3
SDAT 4
AVSS 5
VSSL 6
LCLK1 7
LCLK2 8
16 XOUT
15 _CLK6
14 _CLK5
13 _VSS
12 _LCLK4
11 _VDDL
10 _SCLK
9 _LCLK3
Description
Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal,
regardless of manufacturer, process, performance, or quality
3.3V Voltage Supply
3.3V Analog Voltage Supply
Serial Data Input
Analog Ground
LCLK Ground
Configurable Clock Output 1 at V_DDL level (3.3V or 2.5V)
Configurable Clock Output 2 at V_DDL level (3.3V or 2.5V)
Configurable Clock Output 3 at V_DDL level (3.3V or 2.5V)
Serial Clock Output
LCLK Voltage Supply (2.5V or 3.3V)
Configurable Clock Output 4 at V_DDL level (3.3V or 2.5V)
Ground
Configurable Clock Output 5 (3.3V)
Configurable Clock Output 6 (3.3V)
Reference Output
Note
1. Float XOUT if XIN is driven by an external clock source.
Document #: 38-07104 Rev. *I
Page 2 of 16
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